Tim Creech

I’m a computer engineer at the Intel Compiler Lab, now Compiler Engineering. Before joining Compiler Engineering, I helped research and develop an HPC accelerator for supercomputers as part of Intel Federal.

Previously I was a computer engineering PhD student at the University of Maryland, funded by a NASA Space Technology Research Fellowship. (Formerly “NSTRF,” now called “NSTGRO”.) My advisor was Dr. Rajeev Barua, and my thesis describes “SCAF,” an approach for scheduling malleable parallel processes. I also worked on “AESOP,” an LLVM-based auto-parallelizing compiler. Research areas which I find interesting include parallel computing, compilers, and operating systems.

In the more distant past, I was an undergraduate member of the UMIACS technical staff. I also worked for a year with ARINC (now Collins) in Annapolis, Maryland.